1. Field of the Invention
The present invention relates generally to a circuit, method and program for data queue control that store packets from a plurality of interfaces into the same data queue consisting of a plurality of RAMs, and more particularly, to a circuit, method and program for data queue control that avoid concentration of writing of packets to a specific queue by arranging a buffer queue in front of the RAMs.
2. Description of the Related Art
Conventionally, in a processor board, etc. having a multi-CPU configuration, a system controller is arranged between a plurality of CPUs and resources such as memories and I/O buses, etc. After writing packets arrived from a plurality of interfaces positioned on the resource side into RAMs constituting a queue, the system controller reads those packets and provides data to the CPUs. However, when the throughput of arrival of the packets is lower than the throughput of writing of the RAMs, cases where the writing into the RAMs can not catch up are present. In such cases, a busy signal is issued to the interfaces and the transfer of the packets is discontinued and, therefore, the throughput of the writing into the RAMs is lowered. As a method of solving this problem, as shown in FIG. 1, the throughput of writing into the RAMs is secured by dispersing RAMs that are the target of writing of the packets into by preparing and deploying side by side a plurality of RAMs 200, 202, 204 and 206 and dividing an area for storing packets (one (1) block data area) into sub-blocks for each of the RAMs 200, 202, 204 and 206. FIG. 2 shows a data queue control circuit using the RAMs of FIG. 1 and shows the case where packet storage RAM areas 214-1 to 214-4 obtained by dividing into four (4) sub-blocks are arranged side by side for packets received by six (6) IF latches 208-1 to 208-6. Outputs of the IF latches 208-1 to 208-6 that receive the packets are connected with packet control circuits 210-1 to 210-6 and outputs of the packet control circuits 210-1 to 210-6 are connected with the packet storage RAM areas 214-1 to 214-4 through intervening circuits 212-1 to 212-4. A packet reading circuit 216 is provided to the output side of the packet storage RAM areas 214-1 to 214-4.
However, though such a data queue control method of FIG. 2 has no problem in the case where all of packet data of the amount of one (1) block is stored when packets are stored, that is, the case where all of the packet storage RAM areas 214-1 to 214-4 corresponding to the RAMs 200, 202, 204 and 206 deployed side by side are utilized, a problem arises that the packet storage RAM areas 214-1 to 214-4 deployed side by side can not be effectively utilized and the targets of the writing of the packets concentrate on a specific packet storage RAM area, therefore, the throughput of writing the packets into the RAMs can not be secured in the case where the length of the packets are various, packets having the length shorter than one (1) block are mixed and short packets arrive concentrating because data writing areas of the packets are limited. A data queue control method shown in FIG. 3, for example, is considered in order to solve this problem. In the data queue control circuit of FIG. 3, in addition to the original packet storage Ram areas 214-1 to 214-4, buffer RAMs 218-1 to 218-6 constituting buffer queues for retaining temporarily the packets for the IF latches 208-1 to 208-6 are arranged, and buffer control circuits 220-1 to 220-6 and RAM reading latches 222-1 to 222-6 are provided to the buffer RAMs 218-1 to 218-6. For such a data queue control circuit of FIG. 3, it can be considered to execute control that executes resource management that controls packet transfer using the busy signal, etc. issued from the buffer control circuits 220-1 to 220-6 such that the buffer RAMs 218-1 to 218-6 are not overflowed, reads the packets from the buffer RAMs 218-1 to 218-6 while causing the transmission origin to discontinue the transfer of the packets when necessary, and writes into the packet storage RAM areas 214-1 to 214-4. However, though the data queue control method of FIG. 3 can solve the problem that the writing of packets into the packet storage RAM areas 214-1 to 214-4 can not catch up, the buffer RAMs 218-1 to 218-6, the buffer control circuits 220-1 to 220-6 and the RAM reading latches 222-1 to 222-6 must be provided respectively as many as the number of the interfaces. Therefore the a problem that the circuit scale is considerably increased arises. Furthermore, a problem that degradation of performance is caused to arise because the number of cycles from reception of the packets by the IF latches 208-1 to 208-6 to the writing of the packets into the packet storage RAM areas 214-1 to 214-4 is increased.